兩段式類比至數位轉換器

Two-Step analog-to-Digital Converter

指導教授 : 黃榮堂    研究生 : 鄒家信  機電整合研究所 92年


摘要

  隨著光學式與磁力式儲存設備及各種光線、溫度、顏色與訊號的感應器,甚至有、無線網路通訊與光電整合等轉換技術的高度需求,類比至數位轉換器(Analog to Digital Converter)的應用日趨廣泛,使得對類比至數位轉換器的規格要求也更嚴謹。不但講求速度、精細度與穩定度,更要求了低工作電壓及低耗電,且設計上也日趨多元化,如快閃式、摺疊式、回饋式、平行運算及導線式等不同的電路結構,以因應不同的特性需求。

在本論文中提出了一個高達200 M-Samples/sec 的取樣頻率、8-bit 的取樣寬度的兩段式類比數位轉換器設計架構。在設計結構上,我們採用了平均電阻的方式,消除比較器的偏移電壓。並以 TSMC0.35 μm 2p4m製程來設計製作此兩段式類比至數位轉換器的晶片,面積約為 1000 * 1000 μm2,工作電壓採用 3.3 V的電壓工作模式,以200MHz 的工作頻率、輸入10MHz 弦波測試,可以得到DNL<0.4 LSB, INL<0.5 LSB及有效位元數為 7.5,預期應可作為實際的工業應用。

 

ABSTRACT

 Applications of analog-to-digital converters (ADC) have become widespread as photoelectric devices, magnetic storages, and various sensors, such as light, color, temperature, and signal detectors. Furthermore, specifications of analog-to-digital converters are more stringent as a result of the growing needs for wireless network and communications, as well as photoelectric applications.

In this thesis, a two-step ADC architecture is proposed to have 200 MHz samples rate with 8-bit resolution. We design the high speed architecture analog-to-digital converter by using averaging technology for comparator offset voltage.

We implemented the ADC in TSMC 0.35 μm 2P4M technology. The chip occupied 1*1 mm2 with supply voltage of 3.3V. Through simulation, the chip can work up to 200 MHz as the input sample of 10 MHz sin-wave and has the differential nonlinearity of DNL<0.4 LSB, the integral nonlinearity INL<0.5 LSB, and the efficient number of 7.5 bits.