論文名稱: 高速快閃式類比數位轉換器
[摘要]
隨著光學式與磁力式儲存設備及各種光線、溫度、顏色與訊號的感應器,甚至有、無線網
路通訊與光電整合等轉換技術的高度需求,類比至數位轉換器(Analog to Digital
Converter)的應用日趨廣泛,使得類比對數位轉換器的規格要求也更嚴謹。不但講求速度
、精細度與穩定度,更要求了低工作電壓及低耗電,且設計上也日趨多元化,如快閃式、
摺疊式、回饋式、平行運算及導線式等不同的電路結構,以因應不同的特性需求。
在本論文中提出了一個高達 400 M-Samples/sec 的取樣頻率、6-bit 的取樣寬度的快閃式
類比數位轉換器設計架構。在設計結構上,我們採用了兩組群組交錯式自動歸零設計方法
,以加速單一比較器的比較時間,使比較器電容做充放電的歸零校正。同時,在歸零的時
機配合雙相位切換的調整,使得歸零的程序不會影響到正常比較行為的運作。此外,對產
生參考電壓的電阻串列增加了放大器電路,使之不易產生漂移失真。最後並針對傳統的泡
沫錯誤(Bubble Error)修正電路以複合字串抓取做大幅度的改良,降低MOS電路數量,並提
昇修正的比率。
我們以 TSMC0.25 µm 1p5m製程來設計製作此快閃式類比至數位轉換器的晶片,面積
約為 800 * 1100 μm2,工作電壓採用 3.3 V 及 2.5V 雙電壓工作模式,以 400 MHz 的
工作頻率、輸入 100 MHz 弦波測試,可以得到DNL<0.4 LSB, INL<1.0 LSB及有效位元數
為 5.03,可作為實際的工業應用。最後因為有兩組獨立群組交錯式自動歸零設計方法,減
少了電容的使用,進而大幅減少驅動放大器之功率和晶片面積(152mA)。

 
[摘要]
Applications of analog-to-digital converters (ADC) have become widespread as
photoelectric devices, magnetic storages, and various sensors, such as light,
color, temperature, and signal detectors. Furthermore, specifications of
analog-to-digital converters are more stringent as a result of the growing
needs for wireless network and communications, as well as photoelectric
convergence and conversion knowledge.
In this thesis, a flash ADC architecture is proposed to have 400 MHz samples
rate with 6-bit resolution. We design the high speed architecture analog-to-
digital converter by using two groups interleaved auto-zeroing technology for
shortening the time period in charging to zero for each comparator. The auto-
zeroing process of a comparator would keep normally its comparing operation.
Also, we revise the circuit of the series resistors used for generating
voltage references by adding a post amplifier to avoid effectively the
distortion in voltage floating. Moreover, we instigate the democracy circuit
to over on traditional bubble errors. Thus, we have not only lower the number
of MOS units, but also increase the ration of bubble errors correction.
We implemental the ADC in TSMC 0.25 µm 1P5M technology. The chip
occupied 0.80*1.10 mm2 with both powers of 3.3V and 2.5V. Experimentally, the
chip can work up to 400 MHz as the input sample of 100 MHz sin-wave and has
the differential nonlinearity is DNL<0.4 LSB, the integral nonlinearity is INL<
1.0 LSB ,and the efficient number of 5.03 bits in practical applications.
Moreover, we use two groups interleaved auto-zeroing technology for reducing
the comparators capacitor value, so we can minimize the chip size and power
consumption(152mA).

 
[論文目次]
CONTENTS
中文摘要 .…………………………….……………………………………..…. i
ABSTRACT .………………………………………………………………….... ii
誌謝 .…………………………………………………………………………...iii
CONTENTS.…………..………………………………………………………...iv
Table Content………………………………………………………………………v
Figure Contents ..…………………………….………………………………….vi
Chapter 1 GERNERAL DESCRIPTION .……….…….…….…………………1
Chapter 2 PRACTICAL ASPECTS of Nyquist-Rate ADCs ..4
2.1 Successive-Approximation Converter……………………………………...4
2.2 Pipeline Algorithmic A/D Converter………………………………...……..6
2.3 Iterative Algorithmic A/D Converter.………………………………………6
2.4 Interpolating A/D Converter………………………………………….…….8
2.5 Folding A/D Converter ……………………………………………….……9
2.6 Time-Interleaved A/D Converter……………………………………...…..10
2.7 Oversampling A/D Converter ...……………………………………..……11
2.8 Summary…………………………………………………………………..12
Chapter 3 ADC ARCHITECTURE 14
Chapter 4 CIRCUIT DESCRIPTION 17
4.1 Buffer/Gain Stage 17
4.2 Flash Comparators 20
4.3 Conventional Implementation 28
Chapter 5 METASTABILITY ERRORS 36
Chapter 6 ENCODER 39
Chapter 7 LAYOUT and POWER SUPPLIES 41
Chapter 8 MEASURED RESULTS 43
Chapter 9 CONCLUSION……………………………………………………..46
REFERENCES…………………………………………………………………..47

 
[參考文獻]
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